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CY62148DV30
4-Mbit (512K x 8) MoBL(R) Static RAM
Features
* Temperature Ranges -- Industrial: -40C to 85C -- Automotive-A: -40C to 85C * Very high speed: 55 ns -- Wide voltage range: 2.20V - 3.60V * Pin-compatible with CY62148CV25, CY62148CV30 and CY62148CV33 * Ultra low active power -- Typical active current: 1.5 mA @ f = 1 MHz -- Typical active current: 8 mA @ f = fmax(55-ns speed) * Ultra low standby power * Easy memory expansion with CE, and OE features * Automatic power-down when deselected * CMOS for optimum speed/power * Available in Pb-free and non Pb-free 36-ball VFBGA, Pb-free 32-pin TSOPII and 32-pin SOIC packages
Functional Description[1]
The CY62148DV30 is a high-performance CMOS static RAM organized as 512K words by 8 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery LifeTM (MoBL(R)) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption. The device can be put into standby mode reducing power consumption when deselected (CE HIGH).The eight input and output pins (IO0 through IO7) are placed in a high-impedance state when: * Deselected (CE HIGH) * Outputs are disabled (OE HIGH) * When the write operation is active(CE LOW and WE LOW) Write to the device by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight IO pins (IO0 through IO7) is then written into the location specified on the address pins (A0 through A18). Read from the device by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the IO pins.
Logic Block Diagram
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12
CE WE OE
Data in Drivers
IO 0 IO 1
ROW DECODER
SENSE AMPS
IO 2 IO 3 IO 4 IO 5
512K x 8 ARRAY
COLUMN DECODER
POWER DOWN
IO 6 IO 7
Note: 1. For best practice recommendations, refer to the Cypress application note "System Design Guidelines" on http://www.cypress.com.
Cypress Semiconductor Corporation Document #: 38-05341 Rev. *D
*
198 Champion Court
A13 A14 A15 A16 A17 A18
*
San Jose, CA 95134-1709 * 408-943-2600 Revised January 25, 2007
CY62148DV30
Pin Configuration[2, 3]
36-ball VFBGA Pinout
Top View
32-pin SOIC / TSOP II Pinout
Top View
A0 IO 4 IO 5 VSS VCC IO 6 IO 7 A9
A1 A2
NC WE DNU
A3 A4 A5
A6 A7
A8 IO 0 IO 1 Vcc Vss
A B C D E F G H
A18 OE A10 CE A11
A17 A16 A12 A15 A13
IO 2 IO 3 A14
A17 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 IO 0 IO 1 IO 2 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC A15 A18 WE A13 A8 A9 A11 OE A10 CE IO 7 IO 6 IO 5 IO 4 IO 3
Product Portfolio
Power Dissipation Operating ICC (mA) VCC Range (V) Product CY62148DV30L Range Industrial Min 2.2 Typ[4] 3.0 Max 3.6 Speed (ns) 55 55 70 70 f = 1 MHz Typ[4] 1.5 1.5 1.5 1.5 Max 3 3 3 3 f = fmax Typ[4] 8 8 8 8 Max 15 10 10 10 Standby ISB2 (A) Typ[4] 2 2 2 2 Max 12 8 8 8
CY62148DV30LL Industrial CY62148DV30LL Industrial CY62148DV30LL Automotive-A
Notes: 2. NC pins are not connected on the die. 3. DNU pins have to be left floating or tied to Vss to ensure proper application. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25C.
Document #: 38-05341 Rev. *D
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CY62148DV30
Maximum Ratings
(Exceeding maximum ratings may impair the useful life of the device. For user guidelines, not tested.) Storage Temperature .................................. -65C to +150C Ambient Temperature with Power Applied............................................... 55C to +125C Supply Voltage to Ground Potential ......................................... -0.3V to VCC(max) + 0.3V DC Voltage Applied to Outputs in High-Z State[5, 6] ......................... -0.3V to VCC(max) + 0.3V DC Input Voltage[5, 6] ..................... -0.3V to VCC(max) + 0.3V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... > 200 mA
Operating Range
Product CY62148DV30L CY62148DV30LL CY62148DV30LL Automotive-A -40C to +85C Range Industrial Ambient Temperature -40C to +85C VCC[7] 2.2V to 3.6V
Electrical Characteristics Over the Operating Range
55 ns Parameter VOH VOL VIH Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage IOH = -0.1 mA IOH = -1.0 mA IOL = 0.1 mA IOL = 2.1 mA Test Conditions VCC = 2.20V VCC = 2.70V VCC = 2.20V VCC = 2.70V 1.8 2.2 -0.3 -0.3 -1 -1 Ind'l Ind'l Ind'l Ind'l ISB1 Automatic CE Power-down Current -- CMOS Inputs Automatic CE Power-down Current -- CMOS Inputs CE > VCC-0.2V, VIN>VCC-0.2V, VIN<0.2V) f = fmax (Address and Data Only), f = 0 (OE, and WE), VCC=3.60V CE > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, f = 0, VCC = 3.60V Ind'l Ind'l L LL L LL L LL 8 8 1.5 1.5 2 2 Min 2.0 2.4 0.4 0.4 VCC + 0.3V VCC + 0.3V 0.6 0.8 +1 +1 15 10 3 3 12 8 2 2 2 2 12 8 2 2 8 8 8 8 A 1.5 1.5 3 3 8 8 10 10 1.8 2.2 -0.3 -0.3 -1 -1 Typ[4] Max 2.0 2.4 0.4 0.4 VCC + 0.3V VCC + 0.3V 0.6 0.8 +1 +1 70 ns Min Typ[4] Max Unit V V V V V V V V A A mA mA mA mA mA mA A
VCC = 2.2V to 2.7V VCC= 2.7V to 3.6V
VIL IIX IOZ ICC
Input LOW Voltage Input Leakage Current
VCC = 2.2V to 2.7V VCC= 2.7V to 3.6V GND < VI < VCC
Output Leakage GND < VO < VCC, Output Disabled Current VCC Operating Supply Current f = fmax = 1/tRC VCC = VCC(max) IOUT = 0 mA CMOS levels f = 1 MHz
Auto-A LL
Auto-A LL
Auto-A LL Ind'l Ind'l L LL
ISB2
Auto-A LL
Notes: 5. VIL(min) = -2.0V for pulse durations less than 20 ns. 6. VIH(max) = VCC+0.75V for pulse durations less than 20 ns. 7. Full device AC operation assumes a 100 s ramp time from 0 to VCC(min) and 200 s wait time after VCC stabilization.
Document #: 38-05341 Rev. *D
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CY62148DV30
Capacitance (for all packages)[8]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = VCC(typ) Max 10 10 Unit pF pF
Thermal Resistance
Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 x 4.5 inch, four-layer printed circuit board VFBGA 72 8.86 TSOP II 75.13 8.95 SOIC 55 22 Unit C/W C/W
AC Test Loads and Waveforms
R1 VCC OUTPUT 50 pF INCLUDING JIG AND SCOPE R2 VCC GND 10% ALL INPUT PULSES 90% 90% 10%
Fall time: 1 V/ns
Rise Time: 1 V/ns
Equivalent to:
THEVENIN EQUIVALENT RTH VTH
OUTPUT
Parameters R1 R2 RTH VTH
2.5V (2.2V - 2.7V) 16667 15385 8000 1.20
3.0V (2.7V - 3.6V) 1103 1554 645 1.75
Unit V
Data Retention Characteristics (Over the Operating Range)
Parameter VDR ICCDR tCDR[8] tR[9] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time VCC = 1.5V, CE > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V Ind'l L 0 tRC Ind'l/Auto-A LL Conditions Min Typ[4] Max 1.5 9 6 Unit V A A ns ns
Data Retention Waveform
DATA RETENTION MODE VCC CE
Notes: 8. Tested initially and after any design or process changes that may affect these parameters. 9. Full Device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
1.5V tCDR
VDR > 1.5 V
1.5V tR
Document #: 38-05341 Rev. *D
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CY62148DV30
Switching Characteristics (Over the Operating Range)[10]
55 ns Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Cycle[13] Write Cycle Time CE LOW to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-up to Write End Data Hold from Write End WE LOW to High Z[11, 12] 10 WE HIGH to Low Z[11] 55 40 40 0 0 40 25 0 20 10 70 45 45 0 0 45 30 0 25 ns ns ns ns ns ns ns ns ns ns Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z[11] OE HIGH to High CE LOW to Low CE HIGH to High Z[11,12] 10 20 0 55 0 70 Z[11, 12] Z[11] 5 20 10 25 10 55 25 5 25 55 55 10 70 35 70 70 ns ns ns ns ns ns ns ns ns ns ns Description Min Max Min 70 ns Max Unit
CE LOW to Power-up CE HIGH to Power-up
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[14, 15]
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Notes: 10. Test Conditions for all parameters other than three-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the "AC Test Loads and Waveforms" on page 4. 11. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 12. tHZOE, tHZCE, and tHZWE transitions are measured when the output enter a high impedance state. 13. The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. 14. Device is continuously selected. OE, CE = VIL. 15. WE is HIGH for read cycle.
Document #: 38-05341 Rev. *D
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CY62148DV30
Switching Waveforms (continued)
Read Cycle No. 2 (OE Controlled)[15, 16]
ADDRESS CE tACE tRC
OE
tDOE DATA OUT tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% DATA VALID
tHZOE tHZCE
HIGH IMPEDANCE
tPD 50% ICC ISB
Write Cycle No. 1 (WE Controlled)[17, 18]
tWC ADDRESS CE tAW WE tSA tPWE tSCE
tHA
OE tSD DATA IO NOTE 19 tHZOE DATAIN VALID tHD
Notes: 16. Address valid prior to or coincident with CE transition LOW. 17. Data IO is high impedance if OE = VIH. 18. If CE goes HIGH simultaneously with WE HIGH, the output remains in high-impedance state. 19. During this period, the IOs are in output state and input signals should not be applied.
Document #: 38-05341 Rev. *D
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CY62148DV30
Switching Waveforms (continued)
Write Cycle No. 2 (CE Controlled)[17, 18]
tWC ADDRESS tSCE CE tSA tAW tPWE WE tHA
OE tSD DATA IO DATAIN VALID tHD
Write Cycle No. 3 (WE Controlled, OE LOW)[18]
tWC
ADDRESS
tSCE
CE
tAW tHA tPWE tSD tHD tSA
WE
DATA IO
NOTE 19
tHZWE
DATAIN VALID tLZWE
Truth Table
CE H L L L WE X H H L OE X L H X High Z Data Out (IO0-IO7) High Z Data in (IO0-IO7) Inputs/Outputs Read Output Disabled Write Mode Deselect/Power-down Power Standby (ISB) Active (ICC) Active (Icc) Active (Icc)
Document #: 38-05341 Rev. *D
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CY62148DV30
Ordering Information
Speed (ns) 55 Ordering Code CY62148DV30LL-55BVI CY62148DV30LL-55BVXI CY62148DV30L-55ZSXI CY62148DV30LL-55ZSXI CY62148DV30LL-55SXI 70 CY62148DV30LL-70ZSXI CY62148DV30LL-70ZSXA 51-85081 32-pin SOIC (Pb-free) 51-85095 32-pin TSOP II (Pb-free) 51-85095 32-pin TSOP II (Pb-free) Industrial Automotive-A Package Diagram Package Type 36-ball VFBGA (6 x 8 x 1 mm) (Pb-free) 51-85095 32-pin TSOP II (Pb-free) Operating Range Industrial
51-85149 36-ball VFBGA (6 x 8 x 1 mm)
Contact your local Cypress sales representative for availability of these parts
Package Diagrams
Figure 1. 36-ball VFBGA (6 x 8 x 1 mm), 51-85149
TOP VIEW BOTTOM VIEW A1 CORNER O0.05 M C O0.25 M C A B A1 CORNER O0.300.05(36X) 1 2 3 4 5 6 6 5 4 3 2 1
A B C
A B C
8.000.10
8.000.10
0.75
5.25
D E F G H
D E
2.625
F G H
A B 6.000.10
A
1.875 0.75 3.75 B 6.000.10
0.55 MAX.
0.25 C
0.15(4X)
0.210.05
SEATING PLANE
0.26 MAX.
C
1.00 MAX
0.10 C
51-85149-*C
Document #: 38-05341 Rev. *D
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CY62148DV30
Package Diagrams (continued)
Figure 2. 32-pin TSOP II, 51-85095
51-85095-**
Figure 3. 32-pin (450 MIL) Molded SOIC, 51-85081
16 1
0.546[13.868] 0.566[14.376]
0.440[11.176] 0.450[11.430]
17
32
0.793[20.142] 0.817[20.751]
0.006[0.152] 0.012[0.304]
0.101[2.565] 0.111[2.819]
0.118[2.997] MAX. 0.004[0.102] 0.047[1.193] 0.063[1.600] 0.023[0.584] 0.039[0.990]
0.050[1.270] BSC.
0.004[0.102] MIN. 0.014[0.355] 0.020[0.508] SEATING PLANE
51-85081-*B
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05341 Rev. *D Page 9 of 10
(c) Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY62148DV30
Document History Page
Document Title:CY62148DV30, 4-Mbit (512K x 8) MoBL(R) Static RAM Document Number: 38-05341 REV. ** *A *B ECN NO. 127480 131041 222180 Issue Date 06/17/03 01/23/04 See ECN Orig. of Change HRT CBD AJU Created new data sheet Changed from Advance to Preliminary Changed from Preliminary to Final Added 70 ns speed bin Modified footnote #6 and #12 Removed MAX value for VDR on "Data Retention Characteristics" table Modified input and output capacitance values Added Pb-free ordering information Removed 32-pin STSOP package Added Automotive-A Operating Range Removed SOIC package from Product Offering Updated Ordering Information Table Added SOIC package and its related information Updated Ordering Information Table Description of Change
*C
498575
See ECN
NXR
*D
729917
See ECN
VKN
Document #: 38-05341 Rev. *D
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